Building single chip radio receivers with no off-chip channel filters has recently become popular, probably due to the explosive demand for miniaturized cellular telephone and other wireless network products. Most receivers of this type are designed with either zero intermediate frequency (Zero-IF) or Low-IF architectures, using direct-conversion or near direct-conversion schemes to allow for a low operating frequency with on-chip filters and signal processing circuits.
High integration with more on-chip circuits becomes possible in such architectures, but stringent circuit requirements must be imposed on direct current (DC) offsets, low frequency (1/f) noise, and local oscillator leakages. Some of these requirements are extremely difficult to achieve, with the apparent result that receivers designed around such architectures tend to inferior performance with respect to conventional surface acoustic wave (SAW) based super-heterodyne architectures.
Because of the above-described shortcomings, realizing high performance single chip radio receivers is still an extremely difficult task. There is, therefore, a need in the art for a new radio receiver architecture, which should possess all advantages of the existing architectures without the disadvantages. In addition to a goal of high integration, comparable performance and ease of manufacturing should be factors taken into consideration.